ECE 524 Synthesis & Verification of Digital Circuits
Binary decision diagrams, finite state machines and finite automata. Design automation concepts in logic level synthesis, optimization and verification fo combinational as well as sequential logic. Technology mapping.
Credit Hours: 3 Lecture
Prerequisites: ECE 423,
ECE 425, or consent of instructor
Course Coordinator:
Spyros Tragoudas
Textbooks:
“Synthesis
and Optimization of Digital Circuits, 1st Edition”, Giovanni De
Micheli, McGraw Hill, 1994, ISBN: 0070163332.
References:
Papers from journals and conference proceedings.
Goals:
To provide graduate students with the ability to design or improve automation tools for architectural and logic level synthesis. To provide graduate students with the ability to design or improve automation tools for logic and timing verification.
Projects:
Design the data path of digital system benchmarks. Timing verification of digital circuit benchmarks. Automated synthesis of digital circuit benchmarks.
Computer Tools: Cadence, CUDD, CDFG, LP_solve
Last Review: Spring Semester 2004
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