ECE 425 VLSI Design & Test Automation
Principles of the automated synthesis, verification, testing and layout of Very Large Scale Integration (VLSI) circuits concentrating on the CMOS technology. Resource allocation and scheduling in high-level synthesis. Automation of the logic synthesis for combinational and sequential logic. The physical design automation cycle and CMOS technology considerations. Fault modeling and testing. Timing analysis. Laboratory experience using commercial tools for synthesis and layout.
Credit Hours: 4 (3 Lecture, 1 Laboratory)
Prerequisites: ECE
329 and ECE 345
Textbooks: Professor's notes posted on the web.
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