Department of Electrical and Computer Engineering

RESEARCH INTERESTS AND SPECIALTIES

• Design and Test Automation for VLSI (Very Large Scale Integration) of Digital Systems.

• Routing and Security aspects in Computer Networks.

FEDERAL AND INDUSTRY RESEARCH GRANTS

1. Collaborative Research: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold Logic, National Science Foundation (CCF), 9/1/2007 - 8/31/2010. Principal Investigator: S. Tragoudas.

2. Collaborative Research: Consortium for Embedded Systems, planning grant, National Science Foundation (IIP), 3/13/2007 - 1/31/2008. Principal Investigator: S. Tragoudas.

3. Prototype to Estimate Location of an RF Source, Naval Surface Warfare Center, CRANE, BAA Announcement N00164-05-R-0001, 10/1/2007 - 9/30/2008. Principal Investigator: S. Tragoudas. co-PIs: W. Osborne and F. Harackiewicz.

4. Effect Cause Diagnosis for Path Delay Faults}, Intel Corporation, 6/1/07- 8/15/07. Principal Investigator: S. Tragoudas.

5. Delay Fault Testing in Deep Submicron, Qualcomm Incorporated, 5/16/05 - 5/15/08. Principal Investigator: S. Tragoudas.

6. Path Delay Fault Grading for Large Test Sequences, Intel Corporation, 6/16/05 - 6/15/08. (Principal Investigator: S. Tragoudas.)

7. Effect Cause Diagnosis for Path Delay Faults, Intel Corporation, 6/1/07- 8/15/07. Principal Investigator: S. Tragoudas.

8. Path Delay Fault Grading for Large Test Sequences, Intel Corporation, 6/15/04 - 6/14/2005. (Principal Investigator: S. Tragoudas, co-PI: Th Haniotakis.)

9. Testing for Delay Faults for Digital ICs, Intel Corporation, 01/01/04- 12/31/04. (Principal Investigator: S. Tragoudas, co-PI: Th Haniotakis.)

10. Built--In Test Mechanisms and Embedded Cores, National Science Foundation, Design Automation Program, CCR-9815229 (renamed 0096119), 8/16/98-- 6/31/02. (Principal Investigator: S. Tragoudas, co-PI: D. Kagaris)

11. REU: Built--In Self--Test Mechanisms and Embedded Cores, National Science Foundation (Supplement to CCR-0096119 for undergraduate student involvement), Design Automation Program, (Principal Investigator: S. Tragoudas, co-PI: D. Kagaris), January 2000.

12. REU: Built--In Self--Test Mechanisms and Embedded Cores, National Science Foundation, (Supplement to CCR-9815229 for undergraduate student involvement), Design Automation Program, September 2000. (Principal Investigator: S. Tragoudas, co-PI: D. Kagaris.)

13. Incorporation of Datapath portions in the Controller during High--Level Synthesis, Viewlogic Systems Incorporated, Fremont CA, July 1997. (Principal Investigator: S. Tragoudas.)

14. Built--In Test Pattern Generation Methods, National Science Foundation (Design, Tools and Test program), MIP-9409905, July 1994. (Principal Investigator: S. Tragoudas.)

15. REU (Research Extension for Undergraduates) for Built--In Test Pattern Generation Methods, National Science Foundation, July 1995. (Principal Investigator: S. Tragoudas.)

16. LFSR based Test Pattern Generation, Design Automation Graduate Scholarship (for PhD student support), June 1993. (Principal Investigator: S. Tragoudas.)

EQUIPMENT GRANTS AND GIFTS

1. Synopsys Electronic Design Automation Software, Synopsys Inc., 2/13/07. PI: S.Tragoudas.

2. HP 83000 F330t IC tester, Qualcomm Incorporated, May 2005 (Principal Investigator: S. Tragoudas.)

3. Vertex Xilinx FPGA Boards and Software, Xilinx Corporation (Grant number XUP-18677), for research projects: Detecting Path Delay Faults on RAM-based FPGAs (Principal Investigator: S. Tragoudas) & Mixed-Signal Field Programmable Devices (Principal Investigator: H. Wang.), November 2002.

4. SunBlade 1000: Equipment Grant, National Science Foundation, December 2001. (Principal Investigator: S. Tragoudas.)

5. Sun Blade 1000: Equipment matching grant to NSF, Sun Microsystems, December 2001. (Principal Investigator: S. Tragoudas)

6. Synopsys Design Tool Package, Synopsys Inc., gift for research in VLSI Design Automation (as listed by the SIUC Foundation), adjusted by the Dean of Engineering, January 2000. (Principal Investigator: S. Tragoudas)

PUBLICATIONS IN PROFESSIONAL JOURNALS

1. P. Pintelas and S. Tragoudas, A Comparative Study of Five Language Independent Programming Environments, Journal of Systems Software, vol. 14, pp. 3-15, Elsevier, 1991.

2. S. Tragoudas, F. Makedon and R. Farrell, Circuit Partitioning into Small Sets, Journal of Microprocessors and Microsystems, pp. 471 -- 481, vol. 16, no. 9, Butterworth--Heineman Ltd, 1992.

3. D. Kagaris and S. Tragoudas, Cost-Effective LFSR Synthesis for Optimal Pseudo-Exhaustive Test Sets, IEEE Transactions on VLSI Systems, pp. 526--536, vol. 1, no. 4, 1993.

4. F. Makedon and S. Tragoudas, Approximate Solutions for Graph and Hypergraph Partitioning, Lecture Notes on Series of Computing, vol. 2, special issue on Algorithmic Aspects of VLSI Layout, Editors M. Sarrafzadeh, and D. T. Lee, pp. 133--166, World Scientific Publishing Co., 1993.

5. A. Symvonis and S. Tragoudas, Searching a Pseudo 3-Sided Solid Orthoconvex Grid, International Journal of Foundations of Computer Science, pp. 525--553, no. 4, vol 4, 1993.

6. S. Tragoudas and I. Tollis, River Routing and Density Minimization for Channels with Interchangeable Terminals, Integration, pp. 151--178, vol. 15, Elsevier, 1993.

7. D. Kagaris, F. Makedon and S. Tragoudas, A Method for Pseudo--Exhaustive Test Pattern Generation, IEEE Transactions on Computer--Aided Design of Integrated Circuits and Systems (IEEE--TCAD), vol. 13, no. 9, pp. 1170--1178, 1994.

8. S. Tragoudas, On Channel Routing Problems with Interchangeable Terminals, VLSI Design, vol.2, no. 1, pp. 51--68, Gordon and Breach Science Publishers S.A, 1994.

9. D. Kagaris, S. Tragoudas and D. Bhatia, Pseudo--Exhaustive Built--In TPG for Sequential Circuits, IEEE Transactions on Computer--Aided Design of Integrated Circuits and Systems (IEEE-TCAD), vol. 14, no. 9. pp. 1160--1171, 1995.

10. T. Leighton, F. Makedon, S. Plotkin, C. Stein, E. Tardos and S. Tragoudas, Fast Approximation Algorithms for Multicommodity Flow Problems, Journal of Computer and System Sciences, vol. 50, no. 2, pp.228--243, 1995.

11. D. Kagaris and S. Tragoudas, Avoiding Linear Dependencies in LFSR Test Pattern Generators, Journal of Electronic Testing: Theory and Applications (JETTA), 6, pp. 229--241, 1995.

12. J. Haralambides and S. Tragoudas, The Problem of Partitioning with Node Duplications and its Applications, International Journal of Artificial Intelligence Tools, vol. 3, no. 3, pp. 395--405, 1995.

13. D. Kagaris, S. Tragoudas and A. Majumdar, On the Use of Counters for Reproducing Deterministic Test Sets, IEEE Transactions on Computers, vol. 45, no. 12, pp. 1405--1419, 1996.

14. S. Tragoudas, Board Level Partitioning for Improved Partial Scan, International Journal of High Speed Electronics and Systems, special issue ``High Performance Design Automation for Multi--Chip Modules and Packages'', vol. 6, no.4., pp. 573--594, 1995.

15. S. Tragoudas, Improved approximations for the minimimum cut ratio and the flux, Mathematical Systems Theory journal, 29, pp. 157--167, 1996.

16. D. Kagaris and S. Tragoudas, Retiming Based Partial Scan, IEEE Transactions on Computers, vol. 45, no. 1, pp. 74--87, 1996.

17. S. Tragoudas, Min-Cut Partitioning on Underlying Tree and Graph Structures, IEEE Transactions on Computers, vol. 45, no. 4, pp. 470--474, 1996.

18. D. Kagaris and S. Tragoudas, A Fast Algorithm for Minimizing FPGA Combinational and Sequential Modules, ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 3, pp. 341--351, 1996.

19. J. Haralambides and S. Tragoudas, Bipartitioning into Overlapping Sets, International Journal of Foundations of Computer Science, vol.6. no. 1, pp. 67--88, 1995.

20. D. Kagaris, S. Tragoudas and D. Karayiannis, Nonenumerative Path Delay Fault Coverage Estimation based on Optimal Polynomial--Time Algorithms, IEEE Transactions on Computer--Aided Design of Integrated Circuits and Systems (IEEE-TCAD), vol. 17, no. 3, pp. 309--315, 1997.

21. D. Karayiannis and S. Tragoudas, Implementing and Clustering Modules with Complex Delays, Integration, vol. 22, pp. 39--57, 1997.

22. D. Karayiannis and S. Tragoudas, Clustering Network Modules with Different Implementations for Delay Minimization, VLSI Design, Special issue on High Performance CAD for Interconnections, pp. 1--13, vol. 7, no. 1, 1998.

23. D. Karayiannis and S. Tragoudas, Timing Driven Circuit Implementation, VLSI Design, vol. 7, no. 2, pp. 211--224, 1998.

24. D. Kagaris, G. Pantziou, S. Tragoudas and C. Zaroliagis, Transmissions in a Network with Capacities and Delays, Networks, vol. 33, no. 3, pp. 167--174, 1999.

25. D. Kagaris and S. Tragoudas, On the Design of Optimal Counter--based Schemes for Test Set Embedding, IEEE Transactions on Computer--Aided Design of Integrated Circuits and Systems (IEEE-TCAD), pp. 219--231, vol. 18. no. 2, Feb. 1999.

26. D. Kagaris and S. Tragoudas, Maximum Weighted Independent Sets on Transitive Graphs and Applications, Integration, vol. 27. pp. 77--86, 1999.

27. S. Tragoudas, R. Muezenberger and K. Danhof, Board Level Partitioning for Partial Scan using Fuzzy Logic, IEEE Transactions on Fuzzy Systems, pp. 241--249, vol 7, no. 2, Feb. 1999.

28. S. Tragoudas and D. Karayiannis, A Fast Nonenumerative Automatic Test Pattern Generator for Path Delay Faults, IEEE Transactions on Computer--Aided Design of Integrated Circuits and Systems (IEEE-TCAD), pp. 1050--1058, vol. 18, no 7, July 1999.

29. D.Kagaris and S. Tragoudas, Von Neumann Hybrid Cellular Automata for Generating Deterministic Test Sequences, ACM Transactions on Design Automation of Electronic Systems, vol. 6, no. 3, pp. 308-321, July 2001.

30. D. Kagaris and S. Tragoudas, Computational Analysis of Counter--based Schemes for VLSI Test Pattern Generation, Discrete Applied Mathematics, vol. 110, pp. 227-250, 2001.

31. D. Kagaris. S. Tragoudas, A. Majumdar, Test Set Partitioning for Multi--Weighted Random LFSRs}, Integration, 30 (2000), pp. 65--75.

32. S. Tragoudas, The most reliable data path transmission, IEEE Transactions on Reliability, vol. 50, no. 3, pp. 281--287, Sept. 2001.

33. S. Tragoudas and Y.L. Varol, Disjoint Paths with Length Constraints, International Journal of Computers and their Applications, vol. 9, no.3, pp. 158-167, September 2002.

34. T. Korkmaz, M. Krunz, S. Tragoudas, An efficient Algorithm for Finding a Path Subject to Two Additive Constraints, Journal of Computer Communications (JCC), 25 (2002), pp. 225-238.

35. M.K. Michael and S. Tragoudas, ATPG Tools for Path Delay Faults at the Functional Level, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 7, no. 1, pp. 33-57, 2002.

36. X. Kavousianos, D. Bakalis, D. Nikolos and S. Tragoudas, A New Built-In TPG Method for Random Pattern Resistant Faults, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 21, no.7, July 2002.

37. D. Kagaris and S. Tragoudas, On the Nonenumerative Path Delay Fault Simulation Problem, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 21, no.9, pp. 1095-1100, Sept. 2002.

38. D. Kagaris and S. Tragoudas, LFSR Characteristic Polynomials for Pseudoexhaustive TPG with Low Number of Seeds, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 19, pp. 233-244, June 2003.

39. D. Kagaris and S. Tragoudas, Using a WLFSR to Embed Test Pattern Pairs in Minimum Time, Journal of Electronic Testing: Theory and Applications (JETTA), 18, pp. 305--313, June 2002.

40. S. Padmanaban, M. Michael, S. Tragoudas, Exact Path Delay Fault Coverage with Fundamental ZBDD Operations, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 22, no. 3, pp. 305-316, 2003.

41. S. Tragoudas, N. Denny, Testing for Path Delay Faults Using Test Points, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 8, no. 1, pp.1-10, 2003.

42. S. Padmanaban, S. Tragoudas, An Implicit Path-Delay Fault Diagnosis Methodology, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 22, no. 10, pp. 1399-1408, 2003.

43. M. Michael, Th. Haniotakis, S. Tragoudas, A Unified Framework for Generating All Propagation Functions for Logic Errors and Events, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), pp. 980-987, vol. 23, no. 6, June 2004.

44. J. Deodhar and S. Tragoudas, Implicit Deductive Fault Simulation for Complex Delay Fault Models, IEEE Transactions on VLSI Systems, vol. 12, no. 6, pp. 636-641, June 2004.

45. S. Padmanaban and S. Tragoudas, Efficient Identification of (Critical) Testable Path Delay Faults Using Decision Diagrams, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 1, pp. 77-87, January 2005. (Invited for publication from a paper presented at the Design Automation and Test Conference in Europe (DATE'04).)

46. S. Tragoudas and V. Nagarandal, Embedding Mechanisms for Large Sets of Vectors for Delay Test, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 3, pp. 488-497, March 2005.

47. M.M. Khan and S. Tragoudas, Rewiring for Watermarking Digital Circuit Netlists, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 7, pp. 1132-1136, July 2005.

48. M.D. Galanis, G. Theodoridis, S. Tragoudas, D. Soudris and C. Goutis, A Reconfigurable Coarse-Grain Data-Path for Accelarating Computationally Intensive Kernels, Journal of Circuits, Systems and Computers (JCSC), World Scientific Publishers, vol. 14, no. 9, pp. 877-893, August 2005.

49. M.K. Michael and S. Tragoudas, Function-Based Compact Test Pattern Generation for Path Delay Faults, IEEE Transactions on VLSI Systems, vol. 13, no. 8, pp. 996-1001, August 2005.

50. M.M. Vaseekar Kumar, Spyros Tragoudas, Low Power Test Generation for Path Delay Faults, Journal of Low Power Electronics, vol. 1, no. 2, pp.194-205, August 2005.

51. S. Padmanaban, S. Tragoudas, Implicit Grading for Multiple Path Delay Faults, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 11, issue 2, pp. 346-361, April 2006.

52. M.D. Galanis, G. Theodoridis, S. Tragoudas and C. Goutis, A High Performance Data-Path for Synthesizing DSP Kernels, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 6, pp. 1154-1163, June 2006.

53. D. Kagaris, S. Tragoudas and S. Kuriakose, A Test Architecture for Core-Based SOCs, IEEE Transactions on Computers, vol. 55, no. 2, pp. 137-149, February 2006.

54. S.N. Neophytou, M. Michael and S. Tragoudas, Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 12, pp. 3026--3035, Dec. 2006.

55. M.M.V. Kumar, S. Tragoudas, S. Chakravarty, R. Jayabharathi, Exact Delay Fault Coverage in Sequential Logic under any Delay Fault Model, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 12, pp. 2954-2964, Dec. 2006.

56. M.M.V. Kumar and S. Tragoudas, High Quality Transition Fault ATPG for Small Delay Defects, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD). vol. 26, no. 5, pp. 983-989, May 2007.

57. K.J. Stewart and S. Tragoudas, Managing the power resources of sensor networks with performance considerations, Computer Communications (COMCOM), Elsevier, vol. 30, issue 5, pp. 1122-1135, March 2007.

PRESENTATIONS AT PROFESSIONAL CONFERENCES

PAPERS IN CONFERENCE PROCEEDINGS WITH COMPETITIVE SELECTION PROCESS

1. Approximation Algorithms for VLSI Partitioning Problems, T. Leighton, F. Makedon and S. Tragoudas, Proceedings of the 1990 IEEE International Symposium on Circuits and Systems (ISCAS'90), vol. 4, pp. 2865--2868, New Orleans, Louisiana, May 2-4, 1990. (International.)

2. Interchanging Terminals for Improved Channel Routing, I. Tollis and S. Tragoudas, Proceedings of the 1990 IEEE International Symposium on Circuits and Systems (ISCAS'90), vol. 1, pp. 344--347, New Orleans, Louisiana, May 2--4, 1990. (International.)

3. Approximating the Minimum Net Expansion: Near Optimal Solutions to Circuit Partitioning Problems, F. Makedon and S. Tragoudas, Proceedings of the 16th International Workshop on Graphtheoretic Concepts In Computer Science (WG'90), pp. 140-154, Berlin, Germany, June 1990. (International.)

4. Circuit Partitioning into Small Sets: A Tool to Support Testing with Further Applications, S. Tragoudas, R. Farrell and F. Makedon, Proceedings of the European Conference on Design Automation, (EDAC'91), pp. 518-522, Amsterdam, the Netherlands, February 25--28, 1991. (International.)

5. Faster Approximation Algorithms for Multicommodity Flow Problems, T. Leighton, F. Makedon, S. Plotkin, C. Stein, E. Tardos and S. Tragoudas, Proceedings of the 23th Symposium on the Theory of Computing (STOC'91), pp. 101-112, New Orleans, Louisiana, May 6-8, 1991. (International.)

6. Searching a Solid Pseudo 3 Sided Orthoconvex Grid, A. Symvonis and S. Tragoudas, Proceedings of the 3rd International Symposium on Algorithmic Aspects on Computing: Algorithms and Computation, (ISAAC'92), pp. 188--197, Nagoya, Japan, December 1992. (International.)

7. On Minimizing Hardware Overhead For Pseudoexhaustive Circuit Testability, D. Kagaris, F. Makedon and S. Tragoudas, Proceedings of the 1992 IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD'92), pp. 358--364, Boston, MA, October 11--14, 1992. (International.)

8. A Metric Towards Pseudo-Exhaustive Test Pattern Generation}, D. Kagaris, F. Makedon and S. Tragoudas, Proceedings of the 1992 IEEE International Symposium on Circuits and Systems (ISCAS'92), pp. 379--382, San Diego, CA, March 1992. (International.)

9. Partial Scan with Retiming, D. Kagaris and S. Tragoudas, Proceedings of the 30th ACM/IEEE Design Automation Conference, (DAC'93), pp. 249--254, Dallas, TX, June 14-18, 1993. (International.)

10. Min-Max Cut Graph Partitioning problems, S. Tragoudas, Proceedings 3rd IEEE Great Lakes Symposium on VLSI (GLSV'93), pp. 100--104, Kalamazoo, Michigan, March 5--6, 1993. (National.)

11. Pseudoexhaustive BIST for Sequential Circuits, D. Kagaris, S. Tragoudas and D. Bhatia, Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD'93), pp. 523--527, Boston, MA, October 1993. (International.)

12. A Class of Good Characteristic Polynomials for LFSR Test Pattern Generators, D. Kagaris and S. Tragoudas, Proceedings of the 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD'94), pp. 292--295, Boston, MA, October 1994. (International.)

13. A Design for Testability Technique for LFSR Test Pattern Generators, D. Kagaris and S. Tragoudas, Proceedings of the 12th IEEE VLSI Test Symposium, (VTS'94), IEEE VLSI Test Symposium, pp. 68--73, Cherry Hill, NJ, April 25--28, 1994. (International.)

14. Retiming Algorithms with Applications to VLSI Testability, D. Kagaris and S. Tragoudas, Proceedings of the 4th IEEE Great Lakes Symposium on VLSI, (GLSV'94), pp. 216--221, Notre Dame, Indiana, March 4--5, 1994. (National.) (International.)

15. An Improved Algorithm for the Generalized Min--Cut Partitioning Problem, S. Tragoudas, Proceedings of the 4th IEEE Great Lakes Symposium on VLSI (GLSV'94), pp. 242--247, Notre Dame, Indiana, March 4-5, 1994. (National.)

16. Mathematical Model for Routability Analysis of Field Programmable Gate Arrays (FPGAs), A. Chowdary, D. Bhatia and S. Tragoudas, Proceedings of the 4th IEEE Great Lakes Symposium on VLSI (GLSV'94), pp. 76--79, Notre Dame, Indiana, March 4-5, 1994. (National.)

17. High performance Over--The--Cell routing, J. Crenshaw, N. Sherwani and S. Tragoudas, Proceedings of the 7th International Conference on VLSI Design (VLSI DESIGN'94), Calcutta, India, January 1994. (International.)

18. Uniform Area Timing--Driven Circuit Implementation, D. Karayiannis and S. Tragoudas, 5th IEEE Great Lakes Symposium on VLSI (GLSV'95), pp. 2--7, Buffalo, NY, March 16--18, 1995. (National.)

19. On the Computation of Fast Data Transmissions in Networks with Capacities and Delays, D. Kagaris, G. Pantziou, S. Tragoudas and C. Zaroliagis, Proceedings of the Workshop on Algorithms and Data Structures (WADS'95), pp. 291--302, August 16--18, 1995, Ottawa, Canada (International.)

20. ATPD: An Automatic Test Pattern Generator for Path Delay Faults, D. Karayiannis and S. Tragoudas, Proceedings of the 1996 International Test Conference, (ITC'96), pp. 443--452, Washington D.C., October 21--26, 1996. (International.)

21. A Multiseed Counter TPG with Performance Guarantee, D. Kagaris and S. Tragoudas, Proceedings of the 1996 IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD'96), pp. 34--39, Austin, TX, October 7--9, 1996. (International.)

22. Generating Deterministic Unordered Test Patterns with Counters, D. Kagaris and S. Tragoudas, Proceedings of the 14th IEEE VLSI Test Symposium, (VTS'96), pp. 374--379, Princeton, NJ, April 28--May 1, 1996. (International.)

23. Computing Disjoint Paths with Length Constraints, S. Tragoudas and Y.L. Varol, Proceedings of the 22nd International Workshop on Graph-Theoretic Concepts In Computer Science (WG'96), pp. 375-389, Cadenabbia, Italy, June 1996. (International.)

24. Deterministic Test Set Reproduction by a Counter, D. Kagaris, A. Majumdar and S. Tragoudas, Proceedings of the European Design and Test Conference, (ED&TC'96), pp. 37--41, Paris, France, March 11--14, 1996. (International.)

25. FPGA Module Minimization, D. Kagaris and S. Tragoudas, Proceedings of the 196 International Conference on Computer Design: VLSI in Computers and Processors (ICCD'96), pp. 566--571, Austin, TX, October 1996. (International.)

26. Maximum Weighted Independent Sets on Transitive Graphs and their Applications in Testing and CAD, D. Kagaris and S. Tragoudas, International Conference on Computer--Aided Design (ICCAD'97), pp. 736--740, Nov. 9--13 1997, San Jose, CA. (International.)

27. Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms, D. Kagaris, S. Tragoudas and D. Karayiannis, Proceedings of the 1997 IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD'97), pp. 366--371, Austin, TX, October 12--15, 1997. (International.)

28. Cellular Automata for Generating Deterministic Test Sequences, D. Kagaris and S. Tragoudas, Proceedings of the European Design and Test Conference, (ED&TC'97), pp. 77--81, Paris, France, March 17--20, 1997. (International.)

29. A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults, D. Karayiannis and S. Tragoudas, 16th IEEE VLSI Test Symposium, pp. 440--445, Monterey CA, April 1998. (International.)

30. Multiple Weight--Set Partitioning for Test Set Embedding, D. Kagaris, S. Tragoudas and A. Majumdar, 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'98), pp. 135--143, November 2--4, 1998, Austin TX. (International.)

31. ATPG tools for Delay Faults at the Functional Level, S. Tragoudas and M. Michael, Design Automation and Test in Europe Conference (DATE'99), pp. 631--635, 9--12 March 1999, Munich Germany. (International.)

32. Functional ATPG for Delay Faults, S. Tragoudas and M. Michael, Great Lakes Symposium on VLSI, (GLS--VLSI'99), pp. 16--19, Ann Arbor, MI, March 3--5, 1999. (National.)

33. Embedded Cores using Built-In Mechanisms, D. Kagaris and S. Tragoudas, International Symposium on Circuits and Systems (ISCAS'99), pp. 23-26, vol. I, Orlando FL, May 30--June 2,1999. (International.)

34. Path Delay Fault Coverage is Feasible, S. Tragoudas, Proc. of the 1999 International Test Conference, pp. 201--210, October 1999, Atlantic City, NJ. (International.)

35. LFSR/SR Pseudoexhaustive TPG in Fewer Test Cycles, D. Kagaris and S. Tragoudas, Proceedings of the 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'99), pp. 130--138, 1--3 Nov. 1999, Albuquerque, New Mexico. (International.)

36. Testing for Path Delay Faults using Test Points, S. Tragoudas and N. Denny, Proceedings of the 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'99), pp. 86--94, 1--3 Nov. 1999, Albuquerque, New Mexico. (International.)

37. Methods for On-chip Embedding of Path Delay Test Vectors, Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 84-87, vol. I, May 2000, Geneva, Switzerland. (International.)

38. Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds, D. Kagaris and S. Tragoudas, in the Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD'2000), pp. 42-47, September, 2000, Austin, TX. (International.)

39. An Efficient Algorithm for Finding a Path Subject to Two Additive Constraints, T. Korkmaz, M. Krunz, S. Tragoudas, Proc. SIGMETRICS, pp. 318-327, June 2000, Santa Clara, CA. (International.)

40. Color Counting Technique and Its Applications to Path Delay Fault Coverage, J. Deodhar and S. Tragoudas, Proc. of the IEEE International Symposium on Quality of Electronic Design, pp. 378-383, March 2001, San Jose, CA. (International.)

41. ATPG for Path Delay Faults without Path Enumeration, M. Michael and S. Tragoudas, Proc. of the IEEE International Symposium on Quality of Electronic Design, pp. 384-389, March 2001, San Jose, CA. (International.)

42. Exact Path Delay Grading with Fundamental BDD operations, S. Padmanaban, M. Michael and S.Tragoudas, Proc. of the International Test Conference, Oct. 30-Nov.1 2001, Baltimore MD, pp. 642-651. (International.)

43. Exact Grading of Multiple Path Delay Faults, S. Padmanaban and S. Tragoudas, Proc. Design Automation and Test in Europe, March 2002, Paris, France, pp.84-90. (International.)

44. Nonenumerative Path Delay Fault Diagnosis, S. Padmanaban, S. Tragoudas, Proc. Design Automation and Test in Europe, pp. 322-327, March 3-7, 2003. (International.)

45. Generation of Hazard Identification Functions, M. Michael, S. Tragoudas Proc. International Symposium on Quality of Electronic Design, March 2003. (International.)

46. Interail: Using Existing and Extra Interconnects to Test Core-based SOCs, D. Kagaris, S. Tragoudas, Proceedings of the International On-Line Testing Symposium, pp. 219-224, 7-9 July 2003. (International.)

47. Rewiring for Watermarking Digital Circuits, M.M. Khan, S. Tragoudas, Proc. International Symposium on Quality of Electronic Design (ISQED'04) , March 2004. (International.)

48. An Adaptive Path Delay Fault Diagnosis Methodology, S. Padmanaban and S. Tragoudas, Proc. International Symposium on Quality of Electronic Design (ISQED'04), pp. 143-148, March 2004. (International.)

49. Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults, S. Padmanaban and S. Tragoudas, Proceedings Design Automation and Test in Europe (DATE'04), pp. 322-327, February 2004. (International.)

50. Security Enhancement Through Multiple Path Transmission in Ad Hoc Networks, Th. Haniotakis, S. Tragoudas and C. Kalapodas, Proc. International Conference on Communications (ICC'04), Paris France, June 20-24, 2004. (International.)

51. Circuit Techniques for Field Programmable Analog Array On-Line Testing, H. Wang, S. Kulkarni and S. Tragoudas, Proceedings of the 10th International Mixed Signal Test Workshop (IMSTW'04), pp. 237-244, Portland OR, June 2004. (International.)

52. On-Line Testing Field Programmable Analog Arrays, H. Wang, S. Kulkarni and S. Tragoudas, Proceedings of the 2004 International Test Conference (ITC'04), Session 47.3, Charlotte NC, Nov. 2004. (International.)

53. A Critical Path Selection Method for Delay Testing, S. Padmanaban and S. Tragoudas, Proceedings of the 2004 International Test Conference (ITC'04), Session 9.3, Charlotte NC, Nov. 2004. (International.)

54. Low Power ATPG for Path Delay Faults, M.M. Vaseekar Kumar, S. Padmanaban and S. Tragoudas, Proceedings of the ACM Great lakes Symposium on VLSI (GLSVLSI'04), pp. 389-392, New York NY, April 2004. (National.)

55. Low Power Test Generation for Path Delay Faults using Stability Functions, M.M. Vaseekar Kumar, S. Tragoudas, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2005, pp. 8-12, Chicago IL, April 2005. (National.)

56. Implicit and Exact Path Delay Fault Grading in Sequential Circuits, M. M. Vaseekar Kumar, S. Tragoudas, S. Chakravarty, R. Jayabharathi, Design Automation and Test in Europe (DATE) 2005 Conference, pp. 990-995, Munich, Germany, March 2005. (International.)

57. Test Set Enhancement for Quality Transition Faults using Function-based Methods, M. Michael, S. Neophytou and S. Tragoudas, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2005, pp.3-7, Chicago IL, April 2005. (National.)

58. Design and Evaluation of a Security Scheme for Sensor Networks, K. Stewart, Th. Haniotakis and S. Tragoudas, Proceedings of the International Symposium on Quality of Electronic Design (ISQED'05), pp. 197-201, March 2004. (International.)

59. A Minimum Cut Based Resynthesis Approach, M. Welling, S. Tragoudas, H. Wang, Proceedings of the International Symposium on Quality of Electronic Design (ISQED'05), pp. 202-207, March 2004. (International.)

60. Reduced Test Application Time Based on Reachability Analysis, T. Haniotakis, S. Tragoudas and G.Pani, Proceedings of the International Symposium on Quality of Electronic Design (ISQED'05), pp. 232-237, March 2004. (International.)

61. Functions for Quality Transition Fault Tests, M. Michael, S. Neophytou and S. Tragoudas, International Symposium on Quality of Electronic Design (ISQED'05), pp. 327-333, March 2005. (International.)

62. Towards Finding Path Delay Fault Tests with High Test Efficiency Using ZBDDs, M. Michael, K. Christou and S. Tragoudas, Proceedings of the 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'05), pp. 464-467, San Jose CA, October 2005. (International.)

63. Quality Transition Fault Tests Suitable for Small Delay Defects, M. Kumar and S. Tragoudas, Proceedings of the 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'05), pp. 468-470, San Jose CA, October 2005. (International.)

64. A Security Protocol for Sensor Networks, K. Stewart, Th. Haniotakis and S. Tragoudas, in the Proceedings of the IEEE GLOBECOM 2005, St. Louis MO, 28 Nov.-2 Dec. 2005, to appear. (International.)

65. Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level, A. Abdulrahman, S. Tragoudas, Proc. International Symposium on Quality of Electronic Design (ISQED'06), March 2006. (International.)

66. An improved method for identifying linear dependencies in path delay faults, E. Flanigan, T. Haniotakis and S. Tragoudas, Proc. International Symposium on Quality of Electronic Design (ISQED'06), March 2006. (International.)

67. Evaluation of collapsing methods for fault diagnosis, R. Adapa, M. Michael and S. Tragoudas, Proc. International Symposium on Quality of Electronic Design (ISQED'06), March 2006. (International.)

68. Minimizing reconfiguration logic at the hardware level, K. Raghuraman, H. Wang and S. Tragoudas, Proc. International Symposium on Quality of Electronic Design (ISQED'06), March 2006. (International.)

69. Sub-fault identification for Collapsing in Diagnosis, R. Adapa, S. Tragoudas, M. Michael, Proc. International Symposium on Circuits and Systems (ISCAS'06), May 2006. (International.)

70. Interconnect Testing for Networks on Chip, K. Stewart, S. Tragoudas, Proceedings of the 2006 VLSI Test Symposium (VTS'06), May 2006. (International.)

71. Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding, S. Neophytou, M. Michael, S. Tragoudas, Proceedings of the International On-Line Test Symposium, Lake Como, Italy, June 2006. (International.)

72. Exact At--Speed Delay Fault Grading in Sequential Circuits, M. M. Vaseekar Kumar, S. Tragoudas, S. Chakravarty, R. Jayabharathi, Proceedings of the International Test Conference (ITC'06), October 2006, Santa Clara Convention Center, October 23-26, 2006. (International.)

73. Implicit Critical PDF Generation with Maximal Test Efficiency, C. Kyriakou, M. Michael and S. Tragoudas, Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), October 2006. (International.)

74. A Metric of Fault Tolerance for the Manufacturing Defects of Threshold Logic Gates, S. Dechu, S. Tragoudas, M.K. Goparaju, Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), October 2006. (International.)

75. Accelerating Diagnosis via Dominance Relations between Sets of Faults, R. Adapa, S. Tragoudas. M. Michael, Proceedings of the 25th VLSI Test Symposium, Session 6.B, Berkeley, CA, May 2007. (International.)

CONFERENCES WITH INFORMAL PROCEEDINGS / CONFERNCES WITHOUT PAPER SELECTION PROCESS

1. International IASTED Applied Informatics Conference, 1987.

2. Annual Allerton Conference on Communication, Control and Computing, 1992.

3. Golden West International Conference on Intelligent Systems, 1994.

4. International Conference on Computing and Information, 1994 (Proceedings in J. of Computing and Information, vol. 1, no. 1, 1995).

5. IEEE International Symposium and Workshop on Systems Engineering of Computer Based Systems, 1995.

6. North Atlantic Test Workshop, 1997.

7. ISCA 5th International Conference, 1996.

8. IEEE International On--line Test Workshop, 1998, 1999, \& 2001.

9. IEEE International Performance Computing and Communications Conference, 1999.

10. Southwest Symposium on Mixed Signal Design, 1999 \& 2000.

11. ISCAS International Conference on Computers and their Applications, 1999.

12. 3rd International Workshop on Testing Embedding Core--based Systems, 1999.

13. IEEE International High Level Design Validation and Test Workshop, 1999.

14. IEEE Mediteranian Conference on Control and Automation, 2000.

15. IEEE Wireless Communications and Networking Conference, 2000.

16. International Conference on 3rd Generation Wireless and Beyond, 2001 \& 2002.

17. WSEAS International Conference on Communications 2001, \& 2005 (with proceedings in WSEAS Transactions on Communications, August 2005).

18. WSEAS International Conference on Circuits, 2001, 2002, 2004 (with proceedings in WSEAS Transactions on Circuits and Systems, July 2004), \& 2006 (with proceedings in WSEAS Transactions on Circuits and Systems, August 2006).

19. Hawaii Conference on System Sciences, 1995.

20. Power and Timing Modelling, Optimization and Simulation Workshop, 2004.

21. International SAMOS Workshop, 2004.

22. Field Programmable Logic and Applications Conference, 2004.

23. International WSEAS Conference on Instrumentation, Measurement, Control, Circuits and Systems, 2004 (Proceedings in WSEAS Transactions on Circuits and Systems, July 2004).

24. IEEE Field Programmable Custom Machines (FCCM'04) Symposium, 2004.

25. IEEE International Symposium on Microprocessor Test and Verification, 2004.