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Department of Electrical and Computer Engineering

Faculty

   Faculty                     Adjunct Faculty                 Instructors                    Staff                      Faculty & Instructor Office Hours

Areas of Interest: Embedded systems, power-aware computing, computer architecture, compiler.
Laboratories: Computer Architecture
Courses: ECE 321, ECE 532

ECE News: Compiler-Driven Parallelization for Multi-core Computing, A VLIW Architecture and Compiler Framework for Time Predictability

 

Dr. Wei Zhang
Southern Illinois University Carbondale

Associate Professor, Ph.D. Pennsylvania State University

Telephone: (618) 453-7034
Fax: (618) 453-7972
Office: Engineering E-114
Email: zhang at engr dot siu dot edu
Office Hours
Teaching Schedule

Personal Web Page

Department of Electrical and Computer Engineering
1230 Lincoln Drive
MC 6603
Southern Illinois University Carbondale
Carbondale, IL 62901

Current Research Grants (External)

  • NSF, PI, CSR-EHS: A Dynamic Compilation Framework for Energy Reduction on Mobile Devices.

  • NSF, PI, SGER: A VLIW/Superscalar Heterogeneous Multi-core Architecture and the Compiler Support.

Journal Publications

  1. W. Zhang, B. Allu. Reducing branch predictor leakage energy by exploiting loops. To appear in ACM Transactions on Embedded Computer Systems (TECS).

  2. W. Zhang, Y.-F. Tsai, D. Duarte, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Reducing dynamic and leakage energy in VLIW architectures. To appear in ACM Transactions on Embedded Computer Systems (TECS).

  3. W. Zhang. Replication cache: A small fully associative cache to improve data cache reliability. IEEE Transactions on Computers, Vol. 54, No. 12, pp. 1547-1555, Dec. 2005.

  4. W. Zhang, Y-F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and V. De Leakage-aware compilation for VLIW architectures. Published in IEE Proceedings-Computers and Digital Techniques, Vol. 152, No. 2, pp. 251-261, March 2005.

  5. W. Zhang. Exploiting loop behavior for data cache leakage reduction. Published in Journal of Embedded Computing (JEC): Special Issue on Data Cache Analysis and Optimizations for Embedded Systems. Vol. 1, No. 4, pp. 501-508, IOS Press, 2005.

  6. W. Zhang, M. Kandemir, M. Karakoy, and G. Chen. Reducing data cache leakage energy using a compiler-based approach. Published in ACM Transactions on Embedded Computer Systems (TECS), Vol. 04, Issue 03, pp. 652 - 678, August, 2005.

  7. W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. Reducing instruction cache energy consumption using a compiler-based strategy. Published in ACM Transactions on Architecture and Code Optimization (TACO), page 3-33, Vol. 1, Issue 1, March 2004.

Conference and Workshop Papers

  1. Computing Cache Vulnerability to Transient Errors and Its Implication, W. Zhang, In Proc. of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), Oct. 2005.

  2. Exploiting the Replication Cache to Improve Cache Read Bandwidth Cost Effectively, B. Allu, W. Zhang, M. Kandala, In Proc. of MEDEA'05, in conjunction with PACT'05, Sep. 2005.

  3. Compiler-Guided Register Reliability Improvement against Soft Errors, J. Yan and W. Zhang, In Proc. of the ACM Conference on Embedded Software (EMSOFT), Sep. 2005.

  4. Replica Victim Caching to Improve Reliability of In-Cache Replication, W. Zhang, In Proc. of the 9th Asia-Pacific Computer Systems Architecture Conference (ACSAC'04), page 2-15, Sep, 2004.

  5. Static Next Sub-bank Prediction for Drowsy Instruction Cache, Bramha Allu, Wei Zhang, In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), Washington D.C, Sep, 2004.

  6. Loop-based Leakage Control for Branch Predictors, Wei Zhang, Bramha Allu, In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), Washington D.C, Sep, 2004.

  7. Enhancing Data Cache Reliability by the Addition of a Small Fully-Associative Replication Cache, W. Zhang, In Proc. of the 18th Annual ACM International Conference on Supercomputing, June 2004.

  8. Compiler-Directed Data Cache Leakage Reduction, W. Zhang, In Proc. of the IEEE Computer Society Symposium on VLSI (ISVLSI04), Feb, 2004.

  9. Performance, Energy, and Reliability Tradeoffs in Replicating Hot Cache Lines, W. Zhang, M. Kandemir, A. Sivasubramaniam, and M. J. Irwin, In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'03), San Jose, CA, October 30-November 1, 2003.

  10. ICR: In-Cache Replication for Enhancing Data Cache Reliability, W. Zhang, S. Gurumurthi, M. Kandemir, A. Sivasubramaniam, In Proc. of the Dependable Computing and Communication Symposium (DSN-03), June, 2003.

  11. A Compiler Approach for Reducing Data Cache Energy, W. Zhang, M. Karakoy, M. Kandemir, and G. Chen, In Proc. of the 17th Annual ACM International Conference on Supercomputing (ICS'03), June 2003.

  12. Interprocedural Optimizations for Improving Data Cache Performance of Array-Intensive Embedded Applications, W. Zhang, G. Chen, M. Kandemir, and M. Karakoy, In Proc. of the 40th Design Automation Conference (DAC-03), June, 2003.

  13. Compiler Support for Reducing Leakage Energy Consumption, W. Zhang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and V. De, In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

  14. Data Space Oriented Scheduling In Embedded Systems, M. Kandemir, G. Chen, W. Zhang, and I. Kolcu, In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

  15. Runtime Code Parallelization for On-Chip Multiprocessors, M. Kandemir, W. Zhang, and M. Karakoy, In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

  16. Implementation And Evaluation of An On-Demand Parameter-Passing Strategy for Reducing Energy, M. Kandemir, W. Zhang, and I. Kolcu, In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

  17. Masking the Energy Behavior of DES Encryption, H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, and W. Zhang, In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

  18. Compiler-Directed Instruction Cache Leakage Optimization, Wei Zhang, Jie Hu, Vijay Degalahal, Mahmut Kandemir, N. Vijaykrishnan, and Mary J. Irwin, The 35th Annual International Symposium on Microarchitecture (MICRO-35), November 2002.

  19. Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction, W. Zhang, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte and Y. Tsai, The 34th Annual International Symposium on Microarchitecture (MICRO-34), December 2001.

Book Chapters

  1. M. Kandemir, W. Zhang, M. Karakoy, Dynamic Parallelization of Array Based On-Chip Multiprocessor Applications. In the book Embedded Software for SoC, Edited by A. JERRAYA, published by Kluwer Academic Publishers, Boston, MA, U.S.A, pp.231-244, December 2003.

  2. M. Kandemir, L. Kolcu, W. Zhang, Energy-Aware Parameter Passing, In the book Embedded Software for SoC, Edited by A. JERRAYA, published by Kluwer Academic Publishers, Boston, MA, U.S.A, pp. 305-318, December 2003.

  3. M.Kandemir, G.Chen, W.Zhang, L. Kolcu, Data Space Oriented Scheduling, In the book Embedded Software for SoC, Edited by A. JERRAYA, published by Kluwer Academic Publishers, Boston, MA, U.S.A, pp. 499-512, December 2003.