Department of Electrical and Computer Engineering

Research Interests

• CMOS VLSI

• Fault Tolerance

Publications In Journals

1. G. Laskaris, T. Haniotakis, A. Paschalis and D. Nikolos, "New design method for low-cost TSC checkers for 1-out-of-n and (n-1)-out-of-n codes in MOS implementation,” International Journal of Electronics, vol. 69, no. 6, pp. 805-817, 1990.

2. T. Haniotakis, A. Paschalis and D. Nikolos, "Fast and low cost TSC checkers for 1-out-of-n and (n-1)-out-of-n codes in MOS transistor implementation," International Journal of Electronics, vol.71, no. 5, pp. 781-791, 1991.

3. Th. Haniotakis, A. Paschalis, D. Nikolos and D. Gizopoulos, “Totally Self-Checking Checkers for Borden Codes,” International Journal of Electronics, vol. 76, no. 1, pp. 57-64, 1994.

4. Th. Haniotakis, A. Paschalis, and D. Nikolos, “Efficient Totally Self-Checking Checkers for a Class of Borden Codes,” IEEE Transactions on Computers, vol. 44, no. 11, pp.  1318-1322, 1995.

5. Y. Tsiatouhas, Th. Haniotakis, C. Halatsis and A. Arapoyanni, "Design of Stuck-Open Fault Testable CMOS Complex Gates," Electronics Letters, vol. 32, no. 4, pp 315-317, 1996.

6. Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, A Paschalis and C. Halatsis, "Hierarchical Robust Test Generation for CMOS Circuit Stuck-Open Faults," International Journal of Electronics, vol. 82, no. 1, pp 45-60, 1997.

7. Th. Haniotakis, A. Paschalis, C. Halatsis and G. Philokyprou, “Testable Designs of One-Count Generators,” International Journal of Electronics, vol. 85, no. 5, pp. 629-650, 1998.

In Conferences, Symposiums and Workshops

1. G. Laskaris, T. Haniotakis, A. Paschalis and D. Nikolos, “Efficient Design of TSC Checkers for 1-out-of-N Codes in MOS Transistor Implementation,” Proc. of 12th International Conference on Fault-Tolerant Systems and Diagnostics, Praha, pp. 163-168, 1989.

2. D. Nikolos, A. Paschalis, T. Haniotakis and G. Laskaris "Totally self-checking checkers for optimal t-unidirectional error detecting codes," Proc. of 13th International Conference on Fault-Tolerant Systems and Diagnostics, Varna, pp. 326-331, 1990.

3. Th. Haniotakis, and A Paschalis, “Efficient Structured Design of Robustly Testable CMOS TSC M-out-of-2M Code Checkers,” 1st IEEE International On-Line Testing Workshop, pp. 233-237, Nice, 1995.

4. I. Vogiatzis, D. Nikolos, A. Paschalis, C. Halatsis and Th. Haniotakis, "An Efficient Comparative Concurrent BIST Technique,” Asian Test Symposium (ATS), 1995.

5. Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “Low-Voltage, Built-In Current Sensors for Digital CMOS VLSI Testing,” 4th IEEE International On-Line Testing Workshop, Kapri, 1998.

6. Th. Haniotakis, Y. Tsiatouhas and D. Nikolos, “C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications,” Proc. of IEEE Defect Fault Tolerant (DFT’98) Symposium, Austin, pp. 155-163, Nov. 1998.

7. D.Nikolos, Th. Haniotakis, H.T. Vergos and Y. Tsiatouhas, “Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks”, Proc. of Design, Automation and Test in Europe (DATE’99), pp. 112-116, March 1999.

8. Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou and D. Nikolos, “Novel Domino-CMOS Strongly Code Disjoint and Strongly Fault Secure 1-out-of-3 and 2-out-of-3 Code Checkers”, Proc. of 5th IEEE International On-Line Testing Workshop, Rhodos, pp. 174-178, July 1999.

9. Th. Haniotakis, Y. Tsiatouhas and A. Arapoyanni, “Novel Domino Logic Designs”, Proc. of 6th IEEE Int. Conf. On Electronics, Circuits and Systems (ICECS’99), Pafos, pp. 213-216, Sept. 1999.

10. Th. Haniotakis, H.T. Vergos, Y. Tsiatouhas, D.Nikolos and M. Nicolaidis, “Easily Testable Carry-Save Multipliers with Respect to Path Delay Faults”, Proc. of 2nd Electronic, Circuits and Systems Conference (ECS’99), Bratislava, pp. 13-16, Sept. 1999.

11. Y. Tsiatouhas and Th. Haniotakis, “A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing”, IEEE Defect & Fault Tolerant (DFT’99) Symposium, Albuquerque, Nov. 1999.

12. G. Kaligeros, H.T. Vergos, D.Nikolos, Th. Haniotakis, and Y. Tsiatouhas, “Path Delay Fault Testable Modified Booth Multipliers”, Proc. of XIV DCIS Conference, Palma de Mallorca, pp. 301-306, Nov. 1999.

13. Th. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropoulos, Y. Tsiatouhas and H.T. Vergos, "A Class of Easily Path Delay Fault Testable Circuits", Southwest Symposium on Mixed-Signal Design (SSMSD'00), pp. 164-170, February, 2000.

14. Th. Haniotakis, Y. Tsiatouhas, D. Nikolos and C. Efstathiou, “On Testability of Multiple Precharged Domino Logic”, International Symposium on Quality of Electronic Design (ISQED’00), March 2000.

15. Y. Tsiatouhas, Th. Haniotakis and D. Nikolos, “A Versatile Built-In Self Test Scheme for Delay Fault Testing”, Design, Automation and Test in Europe (DATE’00), March 2000.

16. Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D. Nikolos and A. Arapoyanni, “A New Scheme for Effective IDDQ Testing in Deep Submicron”, Proc. of IEEE Int. Workshop on Defect Based Testing (DBT'00), Montreal, April 2000.

17. Y. Tsiatouhas, Th. Haniotakis and D.Nikolos, “A Compact Built-In Current Sensor for IDDQ Testing”, Accepted for present. in 6th IEEE International On-Line Testing Workshop (IOLTW'00), July 2000.

18. Y. Tsiatouhas, A. Chrisanthopoulos, Th. Haniotakis and G. Kamoulakos, “A New Sense Amplifier for Submicron CMOS Technology Memories”, Accepted for present. in 4th IEEE Circuits, Systems, Communications and Computers Conference (CSCC'00), July 2000.