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Testing for Delay Defects in Embedded Microprocessors

Dr. Spyros Tragoudas has received two grants from Intel Corporation to solve problems related to delay defects in embedded microprocessors.

The research work focuses on the development of fault simulation tools for at-speed application of sequences of test patterns. The path delay models, as well as the transition fault model, are examined. The first exact fault simulation tools for these problem formulations will be developed. Fault simulation will allow for embedded latches. Only pessimistic heuristics exist in the literature for the studied problems. The developed fault simulation tools will allow for accurate fault diagnosis of embedded microprocessors in the temporal domain.