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Journal Publications Calendar Year 2005
Botros N., Akaaboune A. and Alghazo J. “Modeling, Synthesis and Realization of HGH Mechanism Using VHDL and FPGAs,” International Journal on
Modeling & Simulation Vol. 25, No. 4, pp.285-290, November 2005. Lee, Byungje; Harackiewicz, Frances J.; Kong, Ki-Hyun; Byun, Joonho; Yang, Sung-Hyun, “Dual-band dual-circularly-polarized sector antenna for GPS and DAB systems,”
Microwave and Optical Technology Letters, Volume 46, No. 1, pp. 43-46, July 2005. Harackiewicz, Frances J., Jung, Byungwoon, Lee, Byungje, “GPS/PCS dual-band internal antenna with parasitic element,” Microwave and Optical Technology Letters, Volume 46, No. 3, pp. 297-301,
August 2005. B. Lee, F. Harackiewicz, B. Jung, and M-J Park, “Cavity-Backed Slot Antenna Array for the Repeater system of a Satellite Digital Multimedia Broadcasting Service” IEEE Antennas and Wireless Propagation Letters,
Vol. 4, pp. 389-392, December 2005. G. Chang, C.J. Hatziadoniu, and W. Xu, “Modeling Devices with nonlinear Voltage-current Characteristics for harmonic studies”, IEEE Trans. On Power Delivery, Vol. 19, No. 4, pp. 1802-1811, October 2005 J. Phegley, K. Perkins, L. Gupta, & L. Hughes, “Multi-category prediction of multifactorial diseases through risk factor fusion and rank sum selection,” IEEE Transactions on Systems, Man, & Cybernetics – A, Vol. 35, No. 5, pp. 718-726, September 2005. L. Gupta, H. Kook, D.L. Molfese, & K.C. Fadem, “Multi-stimuli multi-channel data and decision fusion strategies for dyslexia prediction using neonatal ERPs,” Pattern Recognition, Vol. 28, No. 11, pp. 2174-2184, November 2005. L. Gupta, B. Chung, M.D. Srinath, D.L. Molfese, & H. Kook “Multi-channel fusion models for the parametric classification of differential brain activity,” IEEE Transactions on Biomedical Engineering, Vol. 52, No. 11, pp. 1869-1881, November 2005. Laknaur, A. and Wang, H., “A Methodology to Perform Online Self-Testing for Field Programmable Analog Array Circuits,” IEEE Trans. on Instrumentation and Measurement, Vol. 54, No. 5, pp.1751-1760, October 2005. D. Kagaris, “Phase Shifter Merging,” Journal of Electronic Testing: Theory and applications, Volume 21, No. 2, pp. 161-168, April 2005. D. Kagaris, “A Unified Method for Phase Shifter Computation,” ACM Transactions on Design Automation of Electronic Systems, Volume l0, No. 1, pp. 157-167, Jan. 2005. Padmanaban S., and S. Tragoudas, “Efficient Identification of (Critical) Testable Path Delay Faults Using Decision Diagrams”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 1, pp. 77-87, January 2005. (Invited paper) Tragoudas S., and V. Nagarandal, “Embedding Mechanisms for Large Sets of Vectors for Delay Test”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 3, pp. 488-497, March 2005. Khan M.M., and S. Tragoudas, “Rewiring for Watermarking Digital Circuit Netlists”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 7, pp. 1132-1136, July 2005. Galanis M.D., G. Theodoridis, S.Tragoudas, D. Soudris, and C. Goutis, “A Reconfigurable Coarse-Grain Data-Path for Accelerating Computationally Intensive Kernels”, Journal of Circuits, Systems and Computers (JCSC), World Scientific Publishers, Vol. 14, No. 9, pp. 877-893, August 2005. Michael M.K., and S. Tragoudas, “Function-Based Compact Test Pattern Generation for Path Delay Faults”, IEEE Transactions on VLSI Systems, Vol. 13, No. 8, pp. 996-1001, August 2005. Kumar V.M.M. and S. Tragoudas, “Low Power Test Generation for Path Delay Faults,” Journal of Low Power Electronics, pp.194-205, Vol. 1, No. 2, August 2005. Stewart K., and S. Tragoudas, “An ILP Based Management Protocol for Wireless Networks”, WSEAS Transactions on Communications, Vol. 4, No. 8, pp. 733-738, August 2005. Kanchumarthy, V. R., Choudhari, T., and Viswanathan, R. “Performance Analysis of Optimum Receivers for Differentially Encoded MPSK in Low SNR,” IEEE Communications Letters, pp. 400-401, May 2005. Zhang, W. “Replication cache: A small fully associative cache to improve data cache reliability.” IEEE Transactions on Computers, Vol. 54, No. 12, pp. 1547-1555, December 2005. Zhang, W., Y-F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and V. De “Leakage-aware compilation for VLIW architectures.” IEE Proceedings-Computers and Digital Techniques, Vol. 152, No. 2, pp. 251-261, March 2005. Zhang, W. “Exploiting loop behavior for data cache leakage reduction.” Journal of Embedded Computing (JEC): Special Issue on Data Cache Analysis and Optimizations for Embedded Systems. Issue 4, July 2005. Zhang, W., M. Kandemir, M. Karakoy, and G. Chen. “Reducing data cache leakage energy using a compiler-based approach.” ACM Transactions on Embedded Computer Systems (TECS), Vol. 04, Issue 03, pp. 652 - 678, August, 2005.
Books & Book Chapters
Botros, N., “HDL Programming Fundamentals: VHDL and Verilog,” Thomson Learning, Da Vinchi Engineering Press, CRM Publisher, ISBN: 58450-855-8 (506 pages), November 2005. Botros, N. and Shell, J., “Modeling and Hardware realization of Biological Mechanisms”, Intelligent Engineering Systems through Artificial Neural Networks, Editors Dagli et al., ASME press, New York, pp. 23-32, October 2005. Varshney, P.K., and Viswanathan, R., “Communications and Radar, Detection in,” in Encyclopedia of Statistical Sciences, 16 Volume Set, 2nd Edition, Kotz, S., Read, C.B., Balakrishnan, N., and Vidakovic, B., Editors, John Wiley, December 2005. Ramaswamy, R., Weng, N., and Wolf, T., “Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures”, Network Processor Design: Issues and Practices, Volume 3, Editors Mark A. Franklin et al., Morgan Kaufmann Publishers, pp. 279-308, February 2005.
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