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Research

Journal Publications Calendar Year 2006

1. Byung-Kil Yu, Byungwoon Jung, Ho-Jun Lee, Frances J. Harackiewicz, and Byungje Lee, “A folded and bent internal loop antenna for GSM/DCS/PCS operation of mobile handset applications,” Microwave and Optical Technology Letters, Vol. 48, No. 3, pp. 463-467, March 2006.

2. H. Rhyu, S. Heo, Y-S Chung, F.J. Harackiewicz and B Lee, “Electrical loop antenna using stacked patches for 433.92 MHz RFID reader,” Electronics Letters, Vol. 42, No. 11, pp. 611-612, May 2006.

3. Byungwoon Jung, Hanphil Rhyu, Young-Joong Lee, Frances J. Harackiewicz, Myun-Joo Park, and Byungje Lee, “Internal folded loop antenna with tuning notches for GSM/GPS/DCS/PCS mobile handset applications,” MOTL, Vol. 48, No. 8, pp. 1501-1504, August 2006.

4. Byungwoon Jung, Hoo Shin, Frances J. Harackiewicz, Myun-Joo Park, and Byungje Lee, “Multiband antenna using a half-wavelength loaded line structure for mobile handheld systems,” MOTL, Vol. 48, No. 9, pp. 1683-1687, September 2006.

5. B. Jung, J-S Lee, M-J Park, Y-S Chung, FJ Harackiewicz and B Lee, “TDMB/AMPS/GSM/DCS/PCS/SDMB internal antenna using parasitic element with switching circuit,” Electronics Letters, Vol. 42, No. 13, pp. 734-736, July 2006.

6. Sung-Joo Kim, Byunggil Yu, Young-Seek Chung, Frances J Harackiewicz and Byungje Lee, “Patch-type radio frequency identification tag antenna mountable on metallic platforms,” MOTL, Vol. 48, No. 12, pp. 2446-2448, December 2006.

7. Botros N. and Shell J. "Towards a Stand-alone Compact Ultrasound Tissue Characterization System” (abstract), Journal of Ultrasonic Imaging, page 19, May 2006.

8. C. J. Hatziadoniu, N. B. Harp, and A. J. Sugg, “Finite-Element Models for Open-Air Power Lines in Broadband PLC”, IEEE Transactions On Power Delivery, Vol. 21, No. 4, pp 1898-1904, October 2006.

9. D. Kagaris, P. Karpodinis, D. Nikolos, “A Method for Accumulator-Based Test-per-Scan BIST,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 11, pp. 2578-2586, November 2006.

10. D. Kagaris, “A Similarity Transform for Linear Finite State Machines,” Discrete Applied Mathematics, Vol. 154, pp 1570-1577, 2006.

11. D. Kagaris, R. Aakuthota, A. Verma, “Maximum Sequence Test Pattern Generators with Irreducible Characteristic Polynomials,” Microprocessors and Microsystems, Vol. 30, No. 2, pp. 117-123, March 2006.

12. D. Kagaris, S. Tragoudas, S. Kuriakose, “InTeRail: A Test Architecture for Core-Based SOCs,” IEEE Transactions on Computers, Vol. 55, No. 2, pp. 137-149, February 2006.

13. A. Mehta, D. Kagaris, R. Viswanathan, “Throughput Performance of an Adaptive ARQ Scheme in Rayleigh Fading Channels,” IEEE Transactions on Wireless Communications, Vol. 5, No. 1, pp. 12-15, January 2006.

14. H. Pongpairoj and F. Pourboghrat, "Real-Time Optimal Control of Flexible Structures Using Subspace Techniques," IEEE Transactions on Control Systems Technology, Vol. 14, No. 6, pp. 1021-1033, Nov. 2006.

15. J. Cheng, M. R. Sayeh, and M. Zargham, “Neural Net Based Models for Clustering,” International Journal of Computational Intelligence Theory and Practice, Volume 1, No. 2, pp. 91-105, 2006.

16. J. Cheng, N. Mogharraban, and M. R. Sayeh, “An Unsupervised Learning Model Based on Differential Equations and Its Application to Gender Recognition,” International Journal of Computational Intelligence Theory and Practice, Volume 1, No.2, pp. 56-65, 2006.

17. R. Viswanathan, “On the Autocorrelation of Complex Envelope of White Noise,” IEEE Transactions on Information Theory, pp. 4298-299, Vol. 52, No. 9, September 2006.

18. A. Laknaur, S. Durbha, and H. Wang, “Built-in-Self-Testing Techniques for Programmable Capacitor Arrays,” Journal of Electronic Testing: Theory and Applications, Vol. 22, No. 6, pp. 449-462, 2006.

19. B. Allu, W. Zhang, “Reducing iTLB Energy Dissipation through Compiler-Directed Resizing,” Journal of Low Power Electronics, Vol. 2, No. 2, pp. 140-147, August 2006.

20. B. Allu, W. Zhang, M. Kandala, “Exploiting the Replication Cache to Improve Cache Read Bandwidth Cost Effectively,” ACM SIGARCH Computer Architecture News, Vol. 34, No.1, pp. 27-32, March 2006.

21. W. Zhang, “Compiler-Guided Next Sub-Bank Prediction for Reducing Instruction Cache Leakage Energy,” Journal of Embedded Computing (JEC): Special Issue on Embedded Processors and Systems: Architectural Issues and Solutions for Emerging Applications, Vol. 2, No. 1, pp. 35-48, 2006.

22. W. Zhang, Y.-F. Tsai, D. Duarte, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “Reducing dynamic and leakage energy in VLIW architectures,” ACM Transactions on Embedded Computer Systems (TECS), Vol. 5, No.1, pp. 1-28, February 2006.

23. K. Limniotis, Y. Tsiatouhas, T. Haniotakis, A. Arapoyanni, "A Design Technique for Energy Reduction in NORA CMOS Logic," Circuits and Systems I: Regular Papers, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Volume 53, No. 12, pp. 2647 – 2655, December 2006.

24. I. Voyiatzis, T. Haniotakis, C. Halatsis, “Algorithm for the generation of SIC pairs and its implementation in a BIST environment," Circuits, Devices and Systems, IEE Proceedings, Volume 153, No. 5, pp. 427 – 432, October 2006.

25. S. Padmanaban, S. Tragoudas, “Implicit Grading for Multiple Path Delay Faults,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 2, pp. 346-361, April 2006.

26. M.D. Galanis, G. Theodoridis, S. Tragoudas and C. Goutis, “A High Performance Data-Path for Synthesizing DSP Kernels,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 6, pp. 1154-1163, June 2006.

27. S. N. Neophytou, M. Michael and S. Tragoudas, “Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 12, pp. 3026-3035, December 2006.

28. M. K. Goparaju and S. Tragoudas, “An ATPG Methodology Using Parametric Fault Model for Defects in Threshold Logic Gate Networks,” WSEAS Transactions on Circuits and Systems, Vol. 5, No. 8, August 2006.

29. M. M. V. Kumar, S. Tragoudas, S. Chakravarty, R. Jayabharathi, “Exact Delay Fault Coverage in Sequential Logic under any Delay Fault Model,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 12, pp. 2954-2964, December 2006.

Books / Chapters

1. Nazeih M. Botros and John R. Shell, “Modeling in Biomedical Engineering”, Intelligent Engineering Systems through Artificial Neural Networks, Editors Dagli et al., Publisher: ASME Press, New York.

2. N. Mohammed and N. Botros, “Leakage-Power Proliferation in Short Channel-Length Caches,” Advances in Systems, Computing Sciences and Software Engineering, Editor T. Sobh, Publisher :Springer.

3. W. Zhang, and B. Allu, “A Compiler-Directed Approach to Reducing Leakage Energy Dissipation for Branch Predictors,” to be published in Handbook on Mobile and Ubiquitous Computing: Innovations and Perspectives, American Scientific Publishers, December 2006 (invited).

4. M.R. Zargham and S. Tragoudas, “Layout, Placement, and Routing,” in the Electrical Engineering Handbook, 3rd Edition, CRC Press, pp. 4-5 to 4-20, 2006.

Conference Proceedings

1. N. Mohammed, N. Botros, W. Zhang, “The Impact of Cache Organization in Optimizing Microprocessor Power Consumption,” CDES06, Las Vegas, June 26-29, 2006.

2. N. Botros and J. Shell, “Biological Mechanism on-a-Chip,” 2nd ASM/IEEE EMBS Bio, Micro and Nanosystems Conference, San Francisco, January 15-18, 2006.

3. R. Vaidyanathan, M. Fargues, L. Gupta, S. Kota, D. Ling & J. West, “A dual-mode human-machine interface for robotic control based on acoustic sensitivity of the aural cavity,” The First IEEE RAS-EMBS International conference on Biomedical Robotics and Biomechatronics, Pisa, Tuscany, Italy, February 2006.

4. R. Vaidyanathan, L. Gupta, H. Kook, and J. West, “A decision fusion pattern classification architecture for robotic interface,” 2006 IEEE International Conference on Robotics and Automation (ICRA), Orlando, Florida, May 2006.

5. D. Kagaris, T. Haniotakis, "Transistor-Level Optimization of Super- Gates" ISQED '06, 7th International Symposium on Quality Electronic Design, March 27-29, 2006.

6. E. Flanigan, T. Haniotakis, S. Tragoudas, "An improved method for identifying linear dependencies in path delay faults," ISQED '06, 7th International Symposium on Quality Electronic Design, March 27-29, 2006.

7. A. Floros, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, "A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism," 13th IEEE International Conference on Electronics, Circuits, and Systems, pp. 692-695, ICECS 2006.

8. S. Matakias, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, "A High Speed Circuit for Concurrent Detection of Soft Errors in CMOS ICs" RADECS 2006.

9. S-J Kim, H. Rhyu, S-H Baek, F.J. Harackiewicz, B. Lee, "UHF Band RFID TagAntenna with Slotted Ground Plane Mountable on Metallic Platforms," 30th Annual Antenna Applications Symposium, September 20-22, 2006, Robert Allerton Park, Monticello, Illinois.

10. J-S Lee, J-W Park, B. Jung, F.J. Harackiewicz, B. Lee, "Wideband Folded Horn Antenna for 20kV Impulse," 30th Annual Antenna Applications Symposium, September 20-22, 2006, Robert Allerton Park, Monticello, Illinois.

11. Frances J. Harackiewicz, Shashi Marikunte, Lizette R. Chevalier, and John Nicklow, "An Innovative Approach to the Advising and Mentoring of Graduate Students," ICEE-2006, Puerto Rico, July 23-28, 2006.

12. Sung-Joon Heo, Hanphil Rhyu, Jin-Seong Lee, Frances J. Harackiewicz, Seung-Hoon Baek, Myun-Joo Park, and Byungje Lee, "Electrical Loop for 433.92MHz Reader Antenna of RFID Systems," 2006 IEEE Antennas and Propagation Society International Symposium, pp.1351-1354, July 9, 2006.

13. Byunggil Yu, Sung-Joo Kim, Byungwoon Jung, Frances J. Harackiewicz, Myun-Joo Park, and Byungje Lee, “Balanced RFID Tag Antenna Mountable on Metallic Plates", 2006 IEEE Antennas and Propagation Society International Symposium, pp. 3237-3240, July 9, 2006.

14. Shashi Marikunte, John Nicklow, Frances Harackiewicz and Lizette Chevalier, "Benefits and Challenges of Training Teaching Assistants," 2006 ASEE Annual Conference, June 2006, Chicago, IL.

15. C.J. Spezia and C.J. Hatziadoniu, “A Maximum Quantity Formulation of the Cournot Game for ISO/POOL Operation,” Proceedings of the 38th North American Power Symposium, Southern Illinois University Carbondale, September 17-19, 2006.

16. D. Nikolos, D. Kagaris, S. Gidaros, “Diophantine-Equation Based Arithmetic Test Set Embedding,” IEEE On-Line Testing Symposium, pp. 194-195, July 2006.

17. J. Kakade, D. Kagaris, “Phase Shifts and Linear Dependencies,” IEEE International Symposium on Circuits and Systems, pp. 1595-1598, May 2006.

18. Siahmakoun, Y. Tang, S. C. Granieri, N. Hoghooghi, S. Teferra, and M. R. Sayeh “Comparison of Wavelength Conversion in SOA and EDFA Fiber Ring Systems,” SPIE Photonics East Proceedings, 2006.

19. A. Abdulrahman, S. Tragoudas “Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level,” Proc. International Symposium on Quality of Electronic Design (ISQED'06), March 2006.

20. E. Flanigan, T. Haniotakis and S. Tragoudas, “An Improved Method for Identifying Linear Dependencies in Path Delay Faults,” Proc. International Symposium on Quality of Electronic Design (ISQED'06), March 2006.

21. R. Adapa, M. Michael and S. Tragoudas, “Evaluation of Collapsing Methods for Fault Diagnosis,” Proc. International Symposium on Quality of Electronic Design (ISQED'06), March 2006.

22. K. Raghuraman, H. Wang and S. Tragoudas, “Minimizing reconfiguration logic at the hardware level,” Proc. International Symposium on Quality of Electronic Design (ISQED'06), March 2006.

23. R. Adapa, S. Tragoudas, M. Michael, “Sub-fault identification for Collapsing in Diagnosis,” Proc. International Symposium on Circuits and Systems (ISCAS'06), May 2006.

24. K. Stewart, S. Tragoudas, “Interconnect Testing for Networks on Chip,” Proceedings of the 2006 VLSI Test Symposium (VTS'06), May 2006.

25. S. Tragoudas and M. Goparaju, “Parametric Fault Model for RTD-based Threshold Logic Gates,” Proceedings of the 10th WSEAS International Conference on Circuits, July 10, 2006.

26. S. Neophytou, M. Michael, S. Tragoudas, “Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding,” Proceedings of the International On-Line Test Symposium, Lake Como, Italy, June 2006.

27. M. M. Vaseekar Kumar, S. Tragoudas, S. Chakravarty, R. Jayabharathi, “Exact At-Speed Delay Fault Grading in Sequential Circuits,” Proceedings of the International Test Conference (ITC'06), October 2006, Santa Clara Convention Center, October 23-26, 2006.

28. C. Kyriakou, M. Michael and S. Tragoudas, “Implicit Critical PDF Generation with Maximal Test Efficiency,” Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), October 2006.

29. S. Dechu, S. Tragoudas, M.K. Goparaju, “A Metric of Fault Tolerance for the Manufacturing Defects of Threshold Logic Gates,” Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'06), October 2006.

30. H. Ray, N. Udar, and R. Viswanathan, “A weighted sum of Gaussian-Derived Pulse Design for UWB,” IEEE Radio and Wireless Symposium, pp. 383-386, San Diego, January 2006.

31. V.R. Kanchumarthy and R. Viswanathan, “Further impacts on the quality of wireless sensor links on decentralized detection performance,” Proceedings of CISS 06, Department of Electrical Engineering, Princeton University, pp. 44-49, Princeton, NJ, 2006.

32. S. Durbha, A. Laknaur, and H. Wang, “Investigating the efficiency of Integrator-Based Capacitor Array Testing Techniques,” Proc. of 24th VLSI Test Symposium, pp. 320-325, Berkeley, CA, May 2006.

33. A. Laknaur and H. Wang, “Design of Window Comparators for Integrator-Based Capacitor Array Testing Circuits,” Proc. of 7th International Symposium on Quality Electronic Design, pp. 531-536, San Jose, CA, 2006.

34. K. Raghuraman, H. Wang, and S. Tragoudas, “Minimizing FPGA Reconfiguration Data at Logic Level,” Proc. of 7th International Symposium on Quality Electronic Design, pp. 219-224, San Jose, CA, 2006.

35. J. Yan, W. Zhang, “WCET Analysis of time-predictable VLIW processors,” In Work-in-Progress (WIP) session of The 27th IEEE Real-Time Systems Symposium, December 2006.

Honors