Journal Papers

J. Yan, W. Zhang. A time-predictable VLIW processor and its
compiler support. In the Journal of Real-Time Systems, Vol 38, No. 1, pp.
67  84, Jan. 2008.

J. Yan, W. Zhang. Exploiting virtual registers to reduce pressure
on real registers. In ACM Transactions on Architecture and Code
Optimization (TACO), Vol. 4, No. 4, pp. 1  18, Jan. 2008.

W. Zhang, B. Allu. Reducing branch predictor leakage energy by
exploiting loops. In ACM Transactions on Embedded Computer Systems (TECS),
Vol. 6, No. 2, pp. 33  50, May 2007.

B. Allu, W. Zhang. Reducing iTLB energy dissipation through
compiler-directed resizing. Published in Journal of Low Power Electronics,
Vol. 2, No. 2, August 2006.

W. Zhang. Compiler-guided next sub-bank prediction for reducing
instruction cache leakage energy. Published in Journal of Embedded
Computing (JEC): Special Issue on Embeded Processors and Systems:
Architectural Issues and Solutions for Emerging Applications, Vol. 2, No.
1, pp. 35-48, 2006.

W. Zhang, Y.-F. Tsai, D. Duarte, N. Vijaykrishnan, M. Kandemir,
and M. J. Irwin. Reducing dynamic and leakage energy in VLIW
architectures. Published in ACM Transactions on Embedded Computer Systems
(TECS), Vol. 5, No. 1, pp. 1-28, February 2006.

W. Zhang. Replication cache: A small fully associative cache to
improve data cache reliability. IEEE Transactions on Computers, Vol. 54, No.
12, pp. 1547-1555, Dec. 2005.

W. Zhang, Y-F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin
and V. De. Leakage-aware compilation for VLIW architectures. Published in IEE
Proceedings-Computers and Digital Techniques, Vol. 152, No. 2, pp. 251-261,
March 2005.

W. Zhang. Exploiting loop behavior for data cache leakage
reduction. Published in Journal of Embedded Computing (JEC): Special Issue
on Data Cache Analysis and Optimizations for Embedded Systems. Vol. 1, No.
4, pp. 501-508, IOS Press, 2005.

W. Zhang, M. Kandemir, M. Karakoy, and G. Chen. Reducing data
cache leakage energy using a compiler-based approach. Published in ACM
Transactions on Embedded Computer Systems (TECS), Vol. 04, Issue 03, pp. 652
- 678, August, 2005.

W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan,
M. J. Irwin. Reducing instruction cache energy consumption using a
compiler-based strategy. Published in ACM Transactions on Architecture and
Code Optimization (TACO), page 3-33, Vol. 1, Issue 1, March 2004.

Conference and Workshop Papers

Efficient code caching to improve performance and energy consumption for Java applications,
Y. Sun, W. Zhang,
In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES08), Oct 2008.

WCET analysis for multi-core processors with shared instruction caches,
J. Yan, W. Zhang,
In Proc. of 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS08), April 2008.

WCET analysis of multi-core processors,
J. Yan, W. Zhang,
In Proc. of the Work-in-Progress (WIP) session of The 28th IEEE Real-Time Systems Symposium, December 2007.

Time-predictable L2 caches for real-time multi-core processors
J. Yan, W. Zhang,
In Proc. of the Work-in-Progress (WIP) session of The 28th IEEE Real-Time Systems Symposium, December 2007.

WCET analysis of instruction caches with prefetching,
J. Yan, W. Zhang,
In Proc. of the ACM SIGPLAN/SIGBED 2007 Conference on Languages, Compilers, and Tools for Embedded Systems, June 2007.

Exploring functional unit design space of VLIW processors for optimizing both performance and energy consumption,
A. Pillai, W. Zhang, L. Yang,
In Proc. of the 4th IEEE International Symposium on Embedded Computing, May 2007.

Detecting VLIW hard errors cost-effectively through a software-based approach,
A. Pillai, W. Zhang, and D. Kagaris,
In Proc. of the 4th IEEE International Symposium on Embedded Computing, May 2007.

An area-efficient approach to improving register file reliability against transient errors,
M. Kandala, W. Zhang, L. Yang,
In Proc. of the 4th IEEE International Symposium on Embedded Computing, May 2007.

Virtual registers: reducing register pressure without enlarging the register file,
J. Yan, W. Zhang,
To Appear In Proc. of the 2007 International Conference on High Performance Embedded Architectures & Compilers, January 2007.

WCET Analysis of time-predictable VLIW processors,
J. Yan, W. Zhang,
To Appear in Work-in-Progress (WIP) session of The 27th IEEE Real-Time Systems Symposium, December 2006.

The impact of cache organization in optimizing microprocessor power consumption,
N. Mohamed, N. Botros, and W. Zhang,
In Proc. of the 2006 International Conference on Computer Design, June 2006.

Selective instruction duplication for improving performance of DIE,
A. Pillai, W. Zhang,
Computing Reliability Issues (HPCRI-2), in conjunction with HPCA, 2006.

Computing Cache Vulnerability to Transient Errors and Its Implication,
W. Zhang,
In Proc. of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), Oct. 2005.

Exploiting the Replication Cache to Improve Cache Read Bandwidth Cost Effectively,
B. Allu, W. Zhang, M. Kandala,
In Proc. of MEDEA'05,  in conjunction with PACT'05, Sep. 2005.

Compiler-Guided Register Reliability Improvement against Soft Errors,
J. Yan and W. Zhang,
In Proc. of the ACM Conference on Embedded Software (EMSOFT), Sep. 2005.

Loop-based iTLB resizing for energy reduction,
B. Allu, W. Zhang,
In Proc. of the second IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (PAC'2), pages 153-159, Sep, 2005.

Enhancing register file reliability through compiler-based approaches,
J. Yan, W. Zhang,
In Proc. of the second IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (PAC'2), pages 170-177, Sep, 2005.

Replica Victim Caching to Improve Reliability of In-Cache Replication,
W. Zhang,
In Proc. of the 9th Asia-Pacific Computer Systems Architecture Conference (ACSAC'04), page 2-15, Sep, 2004.

Static Next Sub-bank Prediction for Drowsy Instruction Cache,
Bramha Allu, Wei Zhang,
In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), Washington D.C, Sep, 2004.

Loop-based Leakage Control for Branch Predictors,
Wei Zhang, Bramha Allu,
In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), Washington D.C, Sep, 2004.

Enhancing Data Cache Reliability by the Addition of a Small Fully-Associative Replication Cache,
W. Zhang,
In Proc. of the 18th Annual ACM International Conference on Supercomputing, June 2004.

Compiler-Directed Data Cache Leakage Reduction,
W. Zhang,
In Proc. of the IEEE Computer Society Symposium on VLSI (ISVLSI04), Feb, 2004.

Performance, Energy, and Reliability Tradeoffs in Replicating Hot Cache Lines,
W. Zhang, M. Kandemir, A. Sivasubramaniam, and M. J. Irwin,
In Proc. of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'03), San Jose, CA, October 30-November 1, 2003.

ICR: In-Cache Replication for Enhancing Data Cache Reliability,
W. Zhang, S. Gurumurthi, M. Kandemir, A. Sivasubramaniam,
In Proc. of the Dependable Computing and Communication Symposium (DSN-03), June, 2003.

A Compiler Approach for Reducing Data Cache Energy,
W. Zhang, M. Karakoy, M. Kandemir, and G. Chen,
In Proc. of the 17th Annual ACM International Conference on Supercomputing (ICS'03), June 2003.

Interprocedural Optimizations for Improving Data Cache Performance of Array-Intensive Embedded Applications,
W. Zhang, G. Chen, M. Kandemir, and M. Karakoy,
In Proc. of the 40th Design Automation Conference (DAC-03), June, 2003.

Compiler Support for Reducing Leakage Energy Consumption,
W. Zhang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and V. De,
In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

Data Space Oriented Scheduling In Embedded Systems,
M. Kandemir, G. Chen, W. Zhang, and I. Kolcu,
In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

Runtime Code Parallelization for On-Chip Multiprocessors,
M. Kandemir, W. Zhang, and M. Karakoy,
In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

Implementation And Evaluation of An On-Demand Parameter-Passing Strategy for Reducing Energy,
M. Kandemir, W. Zhang, and I. Kolcu,
In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

Masking the Energy Behavior of DES Encryption,
H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, and W. Zhang,
In Proc. of the 6th Design Automation and Test in Europe Conference (DATE-03), March, 2003.

Compiler-Directed Instruction Cache Leakage Optimization,
Wei Zhang, Jie Hu, Vijay Degalahal, Mahmut Kandemir, N. Vijaykrishnan, and Mary J. Irwin,
The 35th Annual International Symposium on Microarchitecture (MICRO-35), November 2002.

Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction,
W. Zhang, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte and Y. Tsai,
The 34th Annual International Symposium on Microarchitecture (MICRO-34), December 2001.

Book Chapters

W. Zhang. Compiler-assisted leakage energy reduction for cache memories. To be published in the book Advances in Computers, edited by M. Zelkowitz, published by Elsevier, 2007 (invited).

W. Zhang, B. Allu. A Compiler-directed approach to reducing leakage energy dissipation for branch predictors. To be published in Handbook on Mobile and Ubiquitous Computing: Innovations and Perspectives, American Scientific Publishers, December 2006 (invited).

W. Zhang. Replica victim caching to improve reliability of in-cache replication. In the book Advances in Computer Systems Architecture, Lecture Notes in Computer Science, Springer, Vol 3189, pp.  2-15, 2004.

M. Kandemir, W. Zhang, M. Karakoy, Dynamic Parallelization of Array Based On-Chip Multiprocessor Applications. In the book Embedded Software for SoC, Edited by A. JERRAYA, published by Kluwer Academic Publishers, Boston, MA, U.S.A, pp.231-244, December 2003.

M. Kandemir, L. Kolcu, W. Zhang, Energy-Aware Parameter Passing, In the book Embedded Software for SoC, Edited by A. JERRAYA, published by Kluwer Academic Publishers, Boston, MA, U.S.A, pp. 305-318, December 2003.

M.Kandemir, G.Chen, W.Zhang, L. Kolcu, Data Space Oriented Scheduling, In the book Embedded Software for SoC, Edited by A. JERRAYA, published by Kluwer Academic Publishers, Boston, MA, U.S.A, pp. 499-512, December 2003.

Note: Some of the files above are copyrighted, which can be downloaded only if you are entitled to do so by your  arrangements with the various publishers.